1. Field of the Invention
The present invention relates to semiconductor memory devices, and more specifically to a voltage boosting circuit for generating voltage phases with boosted voltages in a memory device.
2. Description of Related Art
Integrated circuits, and especially memory circuits, often require voltages of different values. The main voltage is the circuit supply voltage (typically 5 V, 3.3 V, or 1.8 V), and higher voltages can be derived from the supply voltage. A boosted voltage is defined as a voltage produced within the integrated circuit with a higher value than the supply voltage itself. Typically, the voltages derived from the main voltage and boosted above the main voltage are not available during the entire operating time of the integrated circuit, but are made available only during predetermined time periods.
Therefore, the boosted voltages take the form of substantially square-wave voltage signals, such as clock signals. Such signals are commonly defined as voltage phases or simply phases (similar to the phases of polyphase voltage circuits) because multiple voltage signals with the same amplitude but different phase shifts are generated. As a result, there are normal voltage phases (i.e., having a square wave with an amplitude equal to the supply voltage) and boosted voltage phases that are identified by a greater voltage amplitude.
Voltage phase generators that produce boosted voltage phases are used in integrated circuits (e.g., to drive booster circuits requiring a high efficiency) mainly with reference the charge transfer from one stage to another. For this purpose. voltage phase generators should be able to output a plurality of voltage signals with different amplitudes and voltage phases. Typically, four voltage phases are provided: two phases FX and FN with an amplitude equal to the supply voltage VDD, and two phases FBX and FBN with boosted voltage that are produced by a voltage boosting circuit (a "bootstrap") from the voltage phases FX and FN, respectively. The voltage phases FX and FN and the voltage phases FBX and FBN are in phase opposition to each other.
FIG. 1a shows a schematic diagram of a conventional booster circuit. The booster circuit 1 has two stages S1 and S2 that receive a supply voltage signal at an input IN and supply a boosted voltage signal from an output OUT. The booster circuit 1 can have several stages for subsequent voltage boosting up to the desired value. The booster circuit 1 is substantially driven by the four voltage phases or clock signals (i.e., two phases FX and FN with an amplitude equal to the supply voltage VDD and two boosted voltage phases FBX and FBN). The boosted voltage phases are obtained from the normal voltage phases FX and FN through the use of a voltage phase generator that contains a voltage boosting or bootstrap circuit. (The voltage phase generator and the voltage boosting circuit are described below with reference to FIG. 1b and FIG. 3.)
The normal voltage phases FX and FN are in phase opposition to each other, as are the two boosted voltage phases FBX and FBN. The booster circuit 1 uses the positive transition of the normal voltage phase FX having an amplitude equal to the supply voltage VDD to raise the voltage on node A up to the value of the supply voltage VDD (i.e., by charging node A through a capacitor CX). The subsequent positive transition of the boosted voltage phase FBX puts transistor M1 in conduction to allow charge transfer from node A to node B. Transistor M1 is driven through the boosted voltage phase FBX by another capacitor CBX. The boosted voltage phase FBX has a higher voltage than the supply voltage VDD so as to prevent a voltage drop across transistor M1 due to the threshold voltage of transistor M1. From node B to the output OUT, there is analogous behavior driven by the normal voltage phase FN and the boosted voltage phase FBN, whose phase opposition will subsequently complete charge transfer from node B to the output OUT.
FIG. 1b shows a voltage phase generator circuit 4 connected to the booster circuit 1 of FIG. 1a. As shown, the voltage phase generator circuit 4 includes a bistable latch LTH that is driven by signals ST1 and ST2 to supply normal voltage phases FX and FN. The boosted voltage phases FBX and FBN are obtained using suitable voltage boosting circuits 2 that receive the normal voltage phases FX and FN and the clock signals CK and CKN of the integrated circuit. The clock signals clock the boosted voltage phases FBX and FBN. FIG. 2 shows timing diagrams of the normal voltage phases FX and FN and the boosted voltage phases FBX and FBN.
FIG. 3 shows a conventional voltage boosting circuit for generating the boosted voltage phases FBX and FBN. As shown, the voltage boosting circuit 2 includes a precharge transistor DP1 that is connected between the supply voltage VDD and a charge node H. The charge mode H receives the voltage phase FX through a capacitor C. The purpose of the capacitor C (like the previous ones) is to raise the voltage on the connected node (i.e., the charge node H) during the positive transition of the voltage phase (i.e., the voltage phase FX). Therefore, a P-channel MOS charge transfer transistor P1 driven by the voltage phase FN is provided between the charge node H and an output FBX.sub.-- OUT. Additionally, the voltage phase FN drives an N-channel discharge transistor N1 that allows the output FBX.sub.-- OUT to discharge during the negative transitions of the voltage phase FX.
The precharge transistor DP1 allows precharging of the charge node H only up to the value VDD-VT, where VT is the threshold voltage of the precharge transistor DP1. A subsequent switch-in of the voltage phase FX brings the boosted voltage phase FBX at the output FBX.sub.-- OUT to the maximum attainable value of 2VDD-VT. FIG. 4 shows the normal voltage phase FX and boosted voltage phase FBX that are produced by the voltage boosting circuit of FIG. 3. The conventional voltage phase generator circuit described above has the drawback of supplying boosted voltage phases with a voltage amplitude that is restricted to 2VDD-VT. This specifically limits the charge transfer speed of the booster circuit stages.